1. Field of the Invention:
The invention relates to a semiconductor device and a method of manufacturing the same, in particular, a semiconductor device having a high breakdown voltage MOS structure and a method of manufacturing the same.
2. Description of the Related Art:
An LDMOS transistor has higher and more stable switching performance and thus it is easier to use than a bipolar type power transistor, as well as IGBT. Therefore, it is widely used in an inverter circuit of a switching power supply or a lighting device such as a DC-DC converter, an inverter circuit of a motor, and so on. An LDMOS is an abbreviation of Lateral Double Diffused Metal Oxide Semiconductor and means a lateral double-diffused MOS.
An LDMOS transistor employs an offset gate structure in which an offset is provided between a gate and a drain for realizing a higher breakdown voltage and miniaturization. FIG. 7 is a cross-sectional view showing a LOCOS offset structure as this type of LDMOS transistor.
As shown in FIG. 7, an N− type drift layer 111, an N+ type drain layer 112, a P type body layer 113 and an N+ type source layer 114 are formed in a surface portion of an N− type semiconductor layer 110 made of an epitaxial layer. The source layer 114 is formed in a surface portion of the body layer 113.
A gate insulation film 115 and a LOCOS insulation film 116 are formed adjoining each other on a surface portion of the semiconductor layer 110, and a gate electrode 117 is formed on the gate insulation film 115 and on a portion of the LOCOS insulation film 116. The drift layer 111 is formed in a surface portion of the semiconductor layer 110 under the LOCOS insulation film 116.
This LDMOS transistor achieves a high drain breakdown voltage since an end portion of the gate electrode 117 is disposed on the thick LOCOS insulation film 116 and the end portion of the gate electrode 117 is disposed away from the drain layer 112.
A high breakdown voltage MOS transistor is disclosed in Japanese Patent Application Publications No. Hei 8-236754, No. Hei 9-223793 and No. 2002-176173.
In the LDMOS transistor in FIG. 7, phosphorus (P) is ion-implanted in a surface portion of the semiconductor layer 110, and then the surface portion of the semiconductor layer 110 is selectively oxidized, thereby forming the LOCOS insulation film 116 and the N− type drift layer 111 under the LOCOS insulation film 116. At the time of this selective oxidation, phosphorus is piled up near the interface between the LOCOS insulation film 116 and the drift layer 111. By this, an N type impurity concentration peak region is formed near the interface.
Therefore, when the LDMOS transistor turns on, almost all the electrons flowing by a potential difference between the source layer 114 and the drain layer 112 run through a surface portion of the drift layer 111 along the interface between the LOCOS insulation film 116 and the drift layer 111 as shown by an arrow in FIG. 7
In this case, a depletion layer is difficult to extend at the interface between the LOCOS insulation film 116 and the drift layer 111 where the N type impurity concentration peak region exists, thereby forming a high electric field region B in the surface portion of the drift layer 111 under the end portion of the gate electrode 117.
Hot electrons accelerated at this high electric field region B and obtaining large energy overpass the potential barrier between the drift layer 111 and the LOCOS insulation film 116 and are trapped in the LOCOS insulation film 116. This causes a reliability problem that the performance of the LDMOS transistor changes with time, such as that the electron concentration of the drift layer 111 decreases to increase the on-resistance.